1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a test circuit of a semiconductor integrated circuit.
2. Description of the Related Art
In a test of a semiconductor integrated circuit, a stress application test is carried out to early detect generation of its initial failure so that defectives products are removed. A circuit for the stress application test is disclosed in Japanese Laid Open Patent Application (JP-P2003-121509A). In this conventional example, a burn-in circuit of the semiconductor integrated circuit has a logic circuit, one or more functional macros, and a built-in self-test circuit. The logic circuit includes a scan chain in an internal circuit. The built-in self-test circuit autonomously carries out a functional macro test provided for every functional macro. In the burn-in circuit of this semiconductor integrated circuit, the logic circuit carries out the burn-in test using the scan chain, and simultaneously the functional macro carries out the burn-in test by means of the testing operation of the built-in self-test circuit. Also, a burn-in scan control circuit is provided to control the burn-in test operation and the scan test operation of the built-in self-test circuit. In this case, a scan test is carried out in the logic circuit and the built-in self-test circuit.
Besides, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2004-251684A). In this conventional example, the semiconductor device includes a memory, a BIST (built-in self-test) circuit, a digital circuit, and a plurality of flip-flops. The BIST circuit and the plurality of flip-flops can operate in parallel to each other. This BIST circuit automatically tests the memory, and the digital circuit receives outputs from the memory. The plurality of flip-flops receive multiple outputs from the digital circuit, and are connected to one after another to constitute a scan chain, in which the received outputs are sequentially produced through a scan shift operation. The BIST circuit applies a stress to the memory at the time of burn-in, and the plurality of flip-flops apply a stress to the digital circuit by performing the scan shift operation at the time of burn-in.
FIG. 1 is a block diagram showing the configuration of this conventional semiconductor device. This conventional semiconductor device includes a memory 120, a logic circuit 110 for accessing the memory 120, flip-flops 116 and 117 as a final stage of memory access in the logic circuit 110, a BIST circuit 130 for testing the memory 120, flip-flops 136 and 137 as a final stage of memory access in the BIST circuit 130, and selecting circuits 124 and 125. The flip-flops 116 and 117 function as an output circuit of the logic circuit 110 and output signals 161 and 162 to the selecting circuits 124 and 125. Besides, the flip-flops 116 and 117 constitute a scan chain in response to a control signal 141, input a serial input signal 151 at the time of a scan path test, and output a serial output signal 152. The flip-flops 136 and 137 output signals 163 and 164 to the selecting circuits 124 and 125 as an output circuit of the BIST circuit when the BIST circuit is operated. In addition, the flip-flops 136 and 137 constitute another scan chain in response to a control signal 142, input a serial input signal 153 at the time of the scan path test, and output a serial output signal 154. The selecting circuits 124 and 125 select either signals 161 and 162, which are outputted from the flip-flops 116 and 117, or signals 163 and 164, which are outputted from the flip-flops 136 and 137, and output the selected signals to the memory 120 as output signals 165 and 166. The memory 120 outputs an output signal 167 to the logic circuit 110 and the BIST circuit 130.
In this conventional semiconductor device, the scan chain is constituted by the logic circuit 110 and the flip-flops 116 and 117 at the time of burn-in test. On the one hand, signals outputted from the BIST circuit 130 are received through the flip-flops 136 and 137 at the rear stage of the BIST circuit to the memory 120. The scan chain, to which the flip-flops 136 and 137 at the rear stage of the BIST circuit are connected, is separated from the scan chain, to which the flip-flops 116 and 117 at the rear stage of the logic circuit 110 are connected. Accordingly, the flip-flops 136 and 137 at the rear stage of the BIST circuit 130 can be operated without performing the scan shift at the time of the burn-in test. Therefore, when the logic circuit 110 is operating the scan shift, it is possible to operate a path from the BIST circuit 130 to the memory 120, so that the memory 120 can be activated from the BIST circuit 130. That is to say, the BIST circuit 130 operates to activate the memory 120, and the scan chain operates in response to the control signal 141 to activate the logic circuit 110 and the flip-flops 116 and 117.
The signals 163 and 164 outputted from the flip-flops 136 and 137 at the rear stage of the BIST circuit 130 activate the memory 120 through the selecting circuits 124 and 125. That is to say, since a path of the BIST circuit 130 for the purpose of accessing the memory 120 does not pass through the flip-flops 116 and 117, it differs from a path of the logic circuit 110 for the purpose of accessing the memory 120. Accordingly, the BIST circuit 130 accesses the memory 120 at a different timing from the logic circuit 110. Therefore, it is not possible to carry out a burn-in test which requires application of sufficient stress to the memory.